1. Field of the Invention
The present invention relates to an image data processing apparatus for processing image data for a two-dimensional discrete cosine transform (DCT) or inverse discrete cosine transform (IDCT).
2. Description of the Prior Art:
Compressing image data for transmission often employs the discrete cosine transform (hereinafter referred to as "DCT") of two-dimensional image data arrayed in 8 rows and 8 columns, and decoding compressed image data into original image data often employs the inverse discrete cosine transform (hereinafter referred to as "IDCT") of two-dimensional image data arrayed in 8 rows and 8 columns. If it is assumed that a matrix of 8.times.8 image data in a real space with elements xi, j is indicated by X, a matrix of 8.times.8 data in a space of spatial frequencies with elements ci, j is indicated by C, and a transform matrix of 8 rows and 8 columns for a DCT is indicated by N, then the following equations (1) are satisfied for DCT, IDCT: EQU DCT: C=(1/4)NXN.sup.t, EQU IDCT: X=(1/4)N.sup.t CN (1).
The matrices N, X, C are defined as follows: ##STR1##
In the above equations (2), a=cos(.pi./16), .alpha.=cos(2.pi./16), b=cos(3.pi./16), c=cos(5.pi./16), .beta.=cos(6.pi./16), d=cos(7.pi./16), and the matrix N.sup.t is a matrix transposed from the matrix N. The DCT is a linear transform from the matrix X to the matrix C, and the IDCT is a linear transform from the matrix C to the matrix X.
One conventional two-dimensional DCT processing circuit with a serial input and a serial output, and one conventional two-dimensional IDCT processing circuit with a serial input and a serial output will be described below with reference to FIGS. 1 and 2, respectively, of the accompanying drawings. The multiplication by 1/4 of coefficients contained in the definition of DCT and IDCT will not be described below as it can easily be carried out by shifting 2 bits.
FIG. 1 shows a conventional two-dimensional DCT processing circuit. The two-dimensional DCT processing circuit includes a first 8.times.8 matrix processing circuit 1 to which there are serially supplied the elements xi, j of a matrix X in a real space. The first 8.times.8 matrix processing circuit 1 then multiplies the matrix X by a matrix N, producing a matrix NX, and serially supplies the 64 elements of the matrix NX to a rearranging circuit 2. The rearranging circuit 2 rearranges the inputted 64 elements of the matrix NX in a predetermined order, and supplies the rearranged 64 elements to a second 8.times.8 matrix processing circuit 3. The second 8.times.8 matrix processing circuit 3 multiplies the supplied matrix NX by a matrix N.sup.t, producing a matrix (NX)N.sup.t, and serially outputs the 64 elements ci, j of the matrix (NX)N.sup.t to a following processing circuit (not shown).
FIG. 2 shows a conventional two-dimensional IDCT processing circuit. The two-dimensional IDCT processing circuit includes a third 8.times.8 matrix processing circuit 4 to which there are serially supplied the elements ci, j of a matrix C in a space of spatial frequencies. The third 8.times.8 matrix processing circuit 4 then multiplies the matrix C by a matrix N.sup.t, producing a matrix N.sup.t C, and serially supplies the 64 elements of the matrix N.sup.t C through a rearranging circuit 5 to a fourth 8.times.8 matrix processing circuit 6. The fourth 8.times.8 matrix processing circuit 6 multiplies the supplied matrix N.sup.t C by the matrix N, producing a matrix (N.sup.t C)N, and serially outputs the 64 elements xi, j of the matrix (N.sup.t C)N.
Generally, a matrix processing circuit for processing serially inputted 8.times.8 matrices and serially outputting the produced matrix requires 8 multipliers. Therefore, each of the conventional two-dimensional DCT and IDCT processing circuits requires 16 (=2.times.8) multipliers. According to a generalization of this requirement, a two-dimensional N.times.N matrix (N is an integer of 2 or more) DCT or IDCT processing circuit requires 2N multipliers. Since the circuit scale of a multiplier is considerably larger than the circuit scale of an adder or a subtractor and also since the overall circuit scale of a processing circuit composed of multipliers is determined substantially depending on the number of the multipliers used, the conventional DCT and IDCT processing circuits have been relatively large in overall circuit scale.
Calculations carried out by multipliers are subject to a round-off error or a truncation error because numbers that are handled are of a limited number of digits. The conventional DCT processing circuit tends to produce a large error due to accumulated round-off errors because a total of two multiplications are effected by the first and second processing circuits 1, 2. The same problem occurs with the conventional IDCT processing circuit.
Japanese Laid-Open Patent Publication No. 62-61159 discloses a technique for reducing the number of multipliers by way of matrix resolution in DCT and IDCT processing apparatus for processing matrices with 8 one-dimensional elements. However, no proposal has been made for reducing the number of multipliers in two-dimensional processing apparatus.